1. Field of the Invention
The present invention relates to a system and method embodied in a clock controller for aligning clocks to free running phase holds and for starting, stopping and pulsing the clocks, and in particular to a clock controller for aligning a plurality of N:1 ratioed clocks to free running phase holds and for starting, stooping and pulsing the ratioed clocks in phase with a master clock.
2. Description of the Related Art
Microprocessors commonly use clock signals to drive a variety of logic circuits within the microprocessor. However, not every logic circuit in the microprocessor necessarily runs at the same clock frequency. Consequently, solutions such as using multiple separate clocks, or single clocks using multiple clock dividers or multipliers and phase lock loops (PLL s) have been used to generate a range of clock frequencies to drive the various logic circuits within the microprocessor.
As the complexity and especially the speed of microprocessors and logic elements has increased, the need for clocks that have better phase alignment between sub-clocks generated by a master clock has also increased. Because the performance of microprocessor circuits can increase as the speed and alignment of clock signals improves, there is a clear need for better phase alignment between clock signals running at various frequencies within the microprocessor. Therefore, what is needed is a system and method for phase alignment of a plurality of clock frequencies, or sub-clocks, that allows the sub-docks to be started, stopped, or pulsed in phase with a master clock.